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Panel: The Great Verification Chiplet Challenge

Chiplet technology represents a paradigm shift in semiconductor design, heralding a new era of more modular and efficient approach to building complex systems-on-chip (SoCs). The latest trend racing through the semiconductor industry is the move to chiplets as companies are invigorating themselves to stay on the cutting edge of technology. Or so it seems as European and U.S. companies embrace a chiplet strategy to overcome Moore’s Law and continue boosting the performance of their latest devices. Overlooked in the heady rush to chiplets are necessary changes to verification to meet the interfacing requirements of a complex chiplet structure.

DVCon Europe presents “The Great Verification Chiplet Challenge” panel featuring Moderator Nick Flaherty who will referee a free-form discussion to unravel the thorny questions about advancing verification to support chiplets and the emerging UCIe interconnect chiplets standard. Panelists from a cross-section of the chip and design verification community will address the chiplet factor facing verification methodologies and why verification must expand beyond functional block tests.The panel will explore strategies for comprehensive verification, including the role of simulation, emulation, and hardware/software co-verification in ensuring the reliability and functionality of chiplet-based systems.

Panelists will conclude by casting a discerning eye toward areas for improvement throughout the verification flow for all chip design. Attendees can expect spirited and lively insights and plenty of good humor.

Audience participation will be encouraged and welcome during what is destined to be an interesting and informative hour-long session.


  • Nick Flaherty, Editor-in-Chief, eeNews Europe


  • Axel Jahnke, MN SoC R&D Manager, Nokia
  • Bodo Hoppe, Distinguished Engineer Hardware Verification, IBM
  • David Kelf, CEO, Breker Verification Systems
  • Moshe Zalcberg, CEO, Veriest
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