Program Grid

All times are in CEST.

Time (CEST) Stream 1 Stream 2 Stream 3 Stream 4 Other Events
8:30 - 9:00

Opening & Welcome

Virtual Experience Room & Networking

9:00 - 10:00

Keynote: Rashid Attar

5G, AI and Compute Platform Innovations for What’s Next

10:00 - 10:30

Virtual Coffee Break

10:30 - 11:30 T1.1 Prototyping Accelerators using Intel® Integrated Simulation Infrastructure with Modeling (Intel® SIM)

Sponsored by:

intel
T2.1 Accelerating Analog/Mixed-Signal Design and Verification through Integrated Rapid Analysis

Sponsored by:

mathworks
T3.1 Accelerate Signoff with JasperGold RTL Designer Apps

Sponsored by:

logo_cadence_0
11:30 - 12:30 T1.2 Artificial Intelligence in ASIC/SOC Verification T2.2 Python and SystemC: A Dream Team for Building and Analyzing Virtual Platformss T3.2 Hardware-Aware, Model-Based Software Development to Speed Up Embedded Designs T4.1 Test Driven Hardware Design and Verification
12:30 - 13:30

Virtual Lunch Break

13:30 - 14:30

Panel:

Anatomy of a Verification Flow

14:30 - 15:30

Keynote: Dr. Petra Färm

Speed Layers: Managing the Exponential Change of Technology

15:30 - 16:00

Virtual Coffee Break

16:00 - 17:00 T1.3 Deep Cycle HW/SW Verification using High-Performance Prototyping Systems

Sponsored by:

Synopsys_Logo
T2.3 AI/ML Accelerator Verification Tutorial: High-Level Verification of C-level design <

Sponsored by:

Siemens-Logo
T3.3 Automated Code Checks to Accelerate Top-Level Design Verification

Sponsored by:

OneSpin Logo
17:00 - 18:00 T1.4 An Update on the UVM-AMS Standard in Accellera

Sponsored by:

OneSpin Logo
T2.4 Boost your Productivity in FPGA & ASIC Design and Verification

Sponsored by:

Sigasi
T3.4 Collaborative, Advanced Fault Analysis: Addressing the Functional Safety Verification Challenges from the Accellera Functional Safety

Sponsored by:

Optima_New_Logo
18:00 - 18:30

Closure Day 1 & Outlook Day 2

Time (CEST) Stream 1 Stream 2 Stream 3 Stream 4 Other Events
8:00 - 8:15

Opening & Welcome

Virtual Experience Room & Networking
8:15 - 9:15

Keynote: Satish Sundaresan

Take a Leap: Virtualization in Future Development

9:15 - 9:30

Virtual Coffee Break

9:30 - 10:00 P1.1 Machine Learning for Coverage Analysis in Design Verification P2.1 Achieving Faster Code Coverage Closure using High-Level Synthesis P3.1 Bringing Reset Domains and Power Domains together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification P4.1 Method for Early Performance Verification of Hardware-accelerated Embedded Processor Systems in RTL Simulation
10:00 - 10:30 P1.2 SimPy and Chips: A Discrete Event Simulation Framework in Python for Large Scale Architectural Modelling of Machine Intelligence Accelerators P2.2 Detection of Glitch-Prone Clock and Reset Propagation with Automated Formal Analysis P3.2 A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling P4.2 System-Level Register Verification and Debug
10:30 - 11:00 P1.3 Optimizing Design Verification using Machine Learning: Doing Better Than Random P2.3 Using HLS to improve Design-for-Verification of Multi-pipeline Designs with Resource Sharing P3.3 Using Dependency Injection Design Pattern in Power Aware Tests P3.4 No Country for Old Men – A Modern Take on Metrics Driven Verification
11:00 - 12:00

Panel

Can ML be the Driver of Next-Generation Verification?

12:00 - 13:00 Virtual Lunch Break Sponsor Sessions
veriest jade design automation lubis eda agnisys agnisys
13:00 - 14:00

Poster Session

14:00 – 15:00 Virtual Coffee Break Sponsor Sessions
corigine cadence fraunhofer amiq eda
15:00 - 15:30 P1.4 A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSS P2.4 Testbench Flexibility as a Foundation for Success P3.4 A Comparison of Methodologies to Simulate Mixed-signal IC P4.4 Machine Learning Based Structure Recognition in Analog Schematics for Constraints Generation
15:30 - 16:00 P1.5 Reuse of System-Level Verification Components within Chip-Level UVM Environments P2.5 Handling Asynchronous Reset(s) Testing by Building Reset-Awareness into UVM Testbench Components P3.5 Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware Prototyping P4.5 Democratizing Formal Verification
16:00 - 16:30 P1.6 A Novel Approach to Functional Test Development and Execution using High-Speed IO P2.6 One Testbench to Rule Them All! P3.6 Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code P4.6 Netlist Paths: A Tool for Front-end Netlist Analysis
16:30 - 17:30

Keynote: Andreas Riexinger

The Mobility of the Future is Software defined – Can Open Technologies help?

17:30 - 18:30

Closing Session & Best Paper/Poster Award Ceremony

Time (CEST)

Title

Author(s) Affiliation(s)
8:00 - 9:00

Welcome & Introduction

Ola Dahl Ericsson
9:00 - 10:00

How to Fork Threads in SystemC Just Like in SystemVerilog and Specman-e

Stefan Tiberiu Petre Independent Verification Consultant
10:00 - 11:00

Multi-cire Debugger Integration and Suspend/Resume

Peter de Jager Intel Corporation, Eindhoven, The Netherlands
11:00 - 12:00

SystemC Community - GitHub, Forums, Websites

Martin Barnasconi 1

Mark Burton 2

1 Accellera

2 GreenSocs

12:00 - 12:30

Update from Accellera SystemC Working Groups

Martin Barnasconi Accellera
12:30 - 13:00

Q&A

All
13:00 - 16:00

Virtual Networking

16:00 - 17:00

SystemC in Hybrid Simulations

Mark Burton 1

Martin Barnasconi 2

1 GreenSocs

2 NXP

17:00 - 18:00

Achieving IC Integrity for SystemC Designs

Rob van Blommestein OneSpin
18:00 - 18:30

Summary and Concluding Discussion

Ola Dahl Ericsson

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