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Shift your HDL design left and keep your eyes on team code metrics in FPGA & ASIC design and verification

Hardware (HDL) development has been adopting tools and best practices from the software development world. Using an Intelligent Development Environment (IDE) to create and maintain SystemVerilog, Verilog and VHDL code is something a lot of design and verification engineers are familiar with. With features like type-time feedback, intelligent autocompletion, and advanced code navigation, how much more can you shift to the left?

A newer trend being adopted from software engineering is the use of continuous integration and continuous deployment systems (CI/CD). A CI/CD system helps assess your team’s code repository in a permanent way. It can automatically build and test your designs and can offer comprehensive reports on the evolution of the HDL code repository.

The CI/CD system makes it easy to start a lot of simulations, synthesis runs, etc. in so-called pipelines. Running many pipelines consumes a lot of resources such as CPU power and software licenses. Therefore, it makes sense to make use of fast, up-front checks on your codebase. These checks can act as a gatekeeper to abort a running pipeline as soon as critical mistakes are uncovered. This will help save valuable resources from being spent in vain.

This tutorial will show new evolutions in IDEs for HDL development and will introduce the concept of integrating gatekeeper functionality into your CI/CD flow.