DVCon Europe 2020 - Technical Program - Day 1 - Tutorials - 27 October 2020

Time (CET)

Stream 1

Stream 2

Stream 3

Stream 4

Other events

8:30 - 9:00

Opening & Welcome

Virtual Experience Rooms
&
Virtual Exhibitors

9:00 - 10:00

Keynote: I Like Being Surrounded by Good Ideas: Any Good Ideas We Can Borrow From The Software World?
Moshe Zalcberg, Chief Executive Officer, Veriest Solutions

10:00 - 10:30

Virtual Coffee Break
Meet us in the Virtual Experience Rooms

10:30 - 11:30

T1.1 Hybrid System Simulation Standards (I)
T2.1 C-SQED: Gap-free Formal Verification of Processor Cores
T3.1 Cross-Level Compliance Testing and Verification for RISC-V

T4.1 Automotive Virtual Prototypes

11:30 - 12:30

T1.2 Hybrid System Simulation Standards (II)

T2.2 Congestion Prediction: Deep Learning on Chip Design Enabling System

T3.2 Introduction to AI Practical Overview to Get Started

 

12:30 - 13:30

Virtual Lunch Break
Meet us in the Virtual Experience Rooms

13:30 - 14:30

Panel: Assessing the Needs and Solutions for a Secure IC Supply Chain
Moderator: Paul Dempsey, Tech Design Forum

14:30 - 15:30

Keynote: The Benefits of Hardware DevOps
Victoria Mitchell, Vice President Systems Engineering, ARM

15:30 - 16:00

Virtual Coffee Break
Meet us in the Virtual Experience Rooms

16:00 - 17:00

T1.3 Application Optimized HW/SW Design & Verification of a Machine Learning SoC

Thank You to Our Sponsor:

T2.3 Meeting ISO 26262 Functional Safety Targets Through Static and Dynamic Fault Analysis

Thank You to Our Sponsor:

T3.3 Beyond Bug Hunting: Verification Coverage from Safety to Certification

Thank You to Our Sponsor:

 

17:00 - 18:00

T1.4 Boost your Productivity in FPGA/ASIC Design and Verification

Thank You to Our Sponsor:

T2.4 Using Simulation Acceleration to Speed Block and Platform Level IP Verification

Thank You to Our Sponsor:

T3.4 Using Models to Shift-Left Verification and Enable Verification IP Re-use Throughout the Design Flow

Thank You to Our Sponsor:

T4.4 Analysis and Verification of safety critical E/E systems and circuits

18:00 - 18:30

Closure Day 1 & Outlook Day 2