DVCon Europe 2020 - Technical Program - Day 2 - 28 October 2020

Time (CET)

Stream 1

Stream 2

Stream 3

Stream 4

Other events

9:00 - 9:15

Opening & Welcome

Virtual Experience Rooms
Virtual Exhibitors

9:15 - 10:15

Keynote: Challenges of a Sustainable Innovative Automotive Computing Architecture
Dr. Matthias Traub, Head of Architecture & Technologies, Volkswagen

10:15 - 10:30

Virtual Coffee Break
Meet us in the Virtual Experience Rooms

10:30 - 11:00

P1.1 Does it pay off to add portable stimulus layer on top of UVM IP block test bench?

P2.1 A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores

P3.1 Boosting Mixed-signal Design Productivity with FPGA-based Methods Throughout the Chip Design Process

P4.1 Enhancing Quality and Coverage of CDC Closure in Intelís SoC Design

11:00 - 11:30

P1.2 Make your Testbenches Run Like Clockwork!

P2.2 Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution

P3.2 SOBEL FILTER: Software Implementation to RTL using High Level Synthesis

P4.2 Static Analysis of SystemC/SystemC-AMS System and Architectural Level Models

11:30 - 12:00

P1.3 A Comprehensive Verification Platform for RISC-V based Processors

P2.3 Model-based Automation of Verification Development for automotive SOCs

P3.3 Single Source System to Register-Transfer Level Design Methodology Using High-Level Synthesis

P4.3 Bit density-based pre-characterization of RAM cells for area critical SOC design

12:00 - 13:00

Virtual Lunch Break
Meet us in the Virtual Experience Rooms

13:00 - 14:00

Poster Session
Virtual Experience Rooms

14:00 - 15:00

Panel: Verification Challenges of an Exascale Supercomputer
Moderator: Jean-Marie Brunet - Mentor, A Siemens Business

15:00 - 15:30

Virtual Coffee Break
Meet us in the Virtual Experience Rooms

15:30 - 16:00

P1.4 Mutable Verification environments through Visitor and Dynamic Register map Configuration

P2.4 Discovering Deadlocks in a Memory Controller IP

P3.4 Mixed Electronic System Level Power/Performance Estimation using SystemC/TLM2.0 Modeling and PwClkARCH library

P4.4 Temporal assertions in SystemC

16:00 - 16:30

P1.5 Facilitating Transactions in VHDL and SystemVerilog

P2.5 How To Verify Encoder And Decoder Designs Using Formal Verification

P3.5 Timing-Aware high level power estimation of industrial interconnect module

P4.5 Accelerating and Improving FPGA Design Reviews Using Analysis Tools

16:30 - 17:00

P1.6 Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For Simulations

P2.6 Using Formal to Prevent Deadlocks

P3.6 Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level

P4.6 Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass

17:00 - 18:00

Keynote: The Future of Compute: Verification in the Era of Heterogeneous Design
Dr. Mike Mayberry, Chief Technology Officer, Intel Corporation

18:00 - 18:30

Closing Session & Best Paper Awards