Software Driven Test of FPGA Prototype

Today’s SoC (ASIC or FPGA) designs are no longer purely hardware; they have recently taken a turn towards containing a significant amount of the software stack. Co-verification of hardware and software is put at greater importance when compared to other requirements in the verification plan. Before such a design is taped-out, it can be verified and validated at speeds near real operating conditions with peripherals and external devices connected using FPGA prototyping boards instead of simulation models. However, preparing a robust FPGA prototype is not a trivial task. It requires strong hardware skills coupled with spending a lot of time in the lab in order to configure and interconnect all required devices with an FPGA base board. It is even more difficult to create a comprehensive test scenario which contains procedures to configure various peripherals and should incorporate various test sequences capturing real life dataflow cases and dependencies. Programming hundreds of registers in proper sequence and then reacting on events, interrupts, and checking status registers is a complex process to implement. This task which is straightforward during simulation where full control over design is assured becomes extremely hard to implement in a FPGA prototype. 

When facing these challenges, verification engineers often connect a microprocessor or microcontroller daughter card to the main FPGA board. The design under test, which is an IP or SoC subsystem, will be connected with some kind of CPU making this way of design seem natural. Having a CPU connected to the design implemented in a FPGA facilitates creating programmatically reconfigurable test scenarios and enables test automation. Moreover, the work of software developers can now be reused because the software stack with device drivers can become a part of the initialization procedure in the hardware test.
Recent evolutions of FPGA technology follows the SoC path known from ASIC designs. We now have hybrid devices like Xilinx Zynq that combine CPU such as ARM Cortex with reconfigurable FPGA in one die. These devices are flexible enough to be used as embedded and software driven testbench for the design prototyped in FPGA. Limited FPGA capacity of Zynq-like devices is not an obstacle in this regard because additional high capacity FPGA parts can be added to the board - for example Xilinx UltraScale whose largest member (XCVU440) estimates to 26 Million ASIC gates.

In this tutorial, we will explain how to build a robust embedded testbench that runs software driven test scenarios. The tutorial will present multiple connectivity options applicable for SoC testing including AMBA AXI Interconnect and demonstrate an example of such with Aldec’s Proto-AXI interface and HES-US-440 prototyping board containing both Virtex Ultrascale XCVU440 for the design and Zynq XC7Z100 for the embedded software driven testbench.

Event ID: 
58117324-d5fb-40f2-9dce-8a04f780e483
Event Type: 
Tutorial
Location: 
Forum 7
Event Time: 
Monday, October 16, 2017 -
14:00 to 15:30
Session Number: 
12
Session Number: 
12
Session Number Suffix: 
T
confID: 
234
Event Sponsor Image URL: 
https://dvcon.org/sites/dvcon.org/files/images/logos/Aldec_Crescent_rgb_sm.png