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Tutorial Presentations

Accelerate Signoff with JasperGold RTL Designer Apps

Bijitendra Mittra, JasperGold Product Engineering team 
Kanwar Pal Singh, JasperGold Product Engineering team 


Accelerating Analog/Mixed-Signal Design and Verification through Integrated Rapid Analysis

Speakers: Ganesh Raj Rathinavel, EMEA Application Engineer for Analog & Mixed Signal Design, MathWorks


AI/ML Accelerator Verification Tutorial: High-Level Verification of C-level design

David Aerne, Siemens EDA
Johnathan Craft, Siemens EDA

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Automated Code Checks To Accelerate Top-Level Design Verification

Speaker: Nicolae Tusinschi, OneSpin

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Boost your productivity in FPGA & ASIC design and verification

Speakers: Bart Brosens, Sigasi


Collaborative, Advanced Fault Analysis: Addressing the Functional Safety Verification Challenges From the Accellera Functional Safety

Speaker: Shesha Sai Kumar, Director of Applications, Optima Design Automation


Deep Cycle HW/SW Verification using High-Performance Prototyping Systems

Speaker: Andy Jolley: Principal Application Engineer Synopsys


Prototyping Accelerators using the Public Intel® Simics® Virtual Platform

Speaker: Jakob Engblom, Intel, Stockholm, Sweden


An Update on the UVM-AMS Standard in Accellera

Speaker: Tom Fitzpatrick, Siemens EDA

Artificial Intelligence in ASIC/SOC Verification

Speaker: Paul Kaunds

Python and SystemC: A dream team for building and analyzing Virtual Platforms

Eyck Jentzsch, MINRES Technologies GmbH, General Manager
Thomas Haber, Toem GmbH, Founder

Test driven Hardware Design and Verification

Moderator: Bodo Hoppe
Speakers: Georg Glaser, Tudor Timisecu, Matthew Ballance, Philipp Wagner & Holger Horbach

Using Hardware-Aware, Model-Based Software Development to Speed Up Embedded Designs

Irina Costachescu, Model Based Design Software Engineer, NXP Semiconductors
Mauro Fusco, Application Engineer – Design Automation and Code Generation, MathWorks