27 - 28 October, 2020

Virtual Conference

Tutorials

Tutorials

Tutorial 1.1, 1.2 Hybrid System Simulation Standards - Purposes, Practices, and Challenges for Interoperable Simulations

Organizer:
Mark Burton - GreenSocs

As complexity increases, the requirements on simulation technology is broadening, especially in terms of interoperability. This workshop is aimed at furthering the understanding of the different simulation standards used across various industrial domains and identifying the main challenges to ensure their interoperability. Towards that goal, the workshop will provide an overview of the industrial usage and requirements of simulation in practise, and present the technical standards supporting them. This workshop will also be an opportunity to share our views and concerns about simulation standards and simulation interoperability, and to identify actions that could be taken collaboratively to address the challenge of Interoperable Simulation.

Agenda:

 

Speakers:
Mark Burton - GreenSocs
Martin Barnasconi - NXP Semiconductors
Rachid Atori - SpaceBel

Jean Casters, Oliver Fourcade - Airbus
Jean-Marie Gauthier - Samares
Andreas Riexinger - Bosch

 

Biographies

Dr Mark Burton is the founder of GreenSocs. Mark graduated from Warwick University with a degree in computer systems engineering. He worked for some years for Inmos (now part of ST microelectornics) and then moved to ACRI (The Advanced Computer Research Institute). He completed a PhD in Artificial Intelligence within Education, specifically focusing on the simulation of high level collaborative learning processes. Mark then worked for ARM becoming the manager of the modeling group. At this time he was also the chair of the OSCI TLM WG. Mark formed GreenSocs with a number of aims, notably to support the entire Electronic System Level industry to better inter-operate, but also to support research and development environments to have more contact with relevant industrial tools and techniques.

Martin Barnasconi is Technical Director System-level Design and Verification Methodologies at NXP Semiconductors. He is driving the innovation and developments related to system-level design, modelling, verification, and flow development for NXP businesses worldwide. Martin has more than 25 years’ experience in this domain and held various positions in Philips Consumer Electronics, Philips Components, Philips Semiconductors and NXP Semiconductors. Martin is Technical Committee Chair at Accellera Systems Initiative, a standardization organization which delivers global standards that improve design and verification productivity for electronics products. In addition is he is chairman of the Accellera SystemC AMS Working Group and IEEE P1666.1 working group, and released SystemC AMS as IEEE standard in 2016. Martin is one of the drivers behind DVCon Europe and the SystemC Evolution Day, and served as General Chair of DVCon Europe in 2014, 2015 and 2018.

Rachid Atori is working since 1994 for SPACEBEL in the space domain and specifically in the modelling & simulation field since 2001. He is now leading the modelling & simulation section since 2012. The addressed sub domains are either related to the models or to the simulators, aka the assembly of models. He is also participating to the SMP standardisation group, which is a ECSS Working Group since 2007. Our main business purpose: making simulators for satellites and launchers. He will try providing some insights related to the SMP standard used now in all of their simulators.

Olivier Fourcade is working in Commercial A/C avionics simulation for 15years. He managed the VISTAS project and set up the EUROCAE working group 97 which aims at defining a plug and play way to make the integration of a virtual or hybrid test bench for A/C Avionics systems. This working group published the ED247 standard to sustain this proposal. It is now officially in rev. A since April 2020. WG97 is working closely with the VHTNG initiative (led by Jean Casteres).

Since 2005, Jean Casteres has been part of the Airbus simulation department developing and managing research projects for the engineering simulators used at Airbus for embedded systems integration. Since 2015 he has been driving the Virtual and Hybrid Testing Next Generation VHTNG research project to propose a continuous test bench architecture for computer embedded systems development and integration. The continuity of the platform being based on a suite of standards to be proposed by the research team. Olivier and Jean will present the work done for the VHTNG and ED247 standard proposals.

Jean-Marie Gauthier obtained a PhD in Computer Science applied to Systems Engineering. He is now an MBSE R&D engineer working at Samares-Engineering since 2016. His main subjects of interest concern systems science applied to modeling and simulation mainly for automotive and aerospace industry. He has published several papers in national and international conference about MBSE and Model-Based Testing (MBT). Finally, he is a course lecturer about SysML, Modelica and FMI at the French ISAE-Supaero Engineering School.

Since end of 2016, Andreas Riexinger is part of the Bosch autonomous driving solutions as a technical product manager automated driving for the Robert Bosch GmbH. He has been working in different areas for over 20 years, in which he has collected experience in the development of embedded software and management of IT projects. Since the foundation of the OpenADx Eclipse Working Group in June 2019, Andreas Riexinger also their speaker. He will give an overview about the role of open source software in autonomous driving.


 

Tutorial 2.1 C-S²QED: Gap-Free Formal Verification of Processor Cores

Organizer:
Keerthikumara Devarajegowda - Infineon Technologies AG

In today’s computer age, processor cores are ubiquitous in every electronic device. Electronic device suppliers build processor cores with a wide range of target applications. Some of these processors are custom built to target specific applications such as signal processing, graphics processing or central processing units that control the operations of a system. Recently, there has been a spike in the design and verification of highly customized processors to address the demands placed by internet-of-things (IoT), artificial intelligence (AI) and other advanced applications.

The processor cores perform computations (by executing instructions), store results and interact with the peripherals devices as specified by an application or a program. The circuitry of processor cores is highly optimized to meet non-functional metrics such as throughput, area and power consumption. Due to the complex nature of these processor cores, ensuring the functional correctness at pre-silicon stage becomes an enormous challenge. Formal verification (FV) exhaustively analyses the design state space and helps to find all logic bugs. However, ensuring that the design space is completely analyzed with a set of properties requires high formal verification expertise and involves laborious manual efforts. As a result, processor verification in industrial practice heavily relies on simulation-based methods, including software and hardware-assisted simulation.

Speakers:
Keerthikumara Devarajegowda - Infineon Technologies AG
Mohammad Rahmani Fadiheh - Technische Universität Kaiserslautern

Biographies

Keerthi Devarajegowda is a formal verification engineer at Infineon Technologies, Munich. He received his MSc degree from TU Kaiserslautern in 2016. Currently he is awaiting his PhD graduation. His research interests include formal verification methods and hardware domain specific languages.

 

 

 

Mohammad Fadiheh received his MSc in Electrical and Computer Engineering from TU Kaiserslautern in 2017.
Mohammad is currently a PhD candidate at Electronic Design Automation group at the same university.
His research interests include  functional and security verification of Hardware based on formal methods.

 


 

Tutorial 3.1 Cross-Level Compliance Testing and Verification for RISC-V

Organizers:
Vladimir Herdt - DFKI GmbH Bremen
Daniel Große - Johannes Kepler University Linz
Eyck Jentzsch - MINRES Technologies

RISC-V is an open and royalty-free Instruction Set Architecture (ISA) that gained enormous momentum in both academia and industry in recent years. The major goal of the RISC-V ISA is to provide a path to a new era of processor innovation via open standard collaboration. RISC-V became a game changer for embedded systems in several application areas including e.g. IoT and Edge devices. RISC-V features an extremely modular and extensible design that provides enormous flexibility in building application specific solutions that can leverage custom extensions and only include features that are really required. However, this enormous flexibility also leads to a significantly increased risk of introducing SW incompatibilities between different RISC-V implementations, thus causing fragmentation of the RISC-V ecosystem. This very important problem is addressed with compliance testing. More precisely, compliance testing checks whether registers are missing, modes are not there, instructions are absent, as well as the presence of only those instructions which are part of the selected ISA. If the compliance test passes for a CPU, the HW/SW contract is maintained and the SW will be portable between implementations. Note that compliance testing is not design verification. In contrast to compliance testing, the goal of verification is to find errors in the CPU implementation and ultimately prove that an implementation is correct. Thus, thorough verification has to be performed later in the development phase and is complementary to compliance testing.

In this tutorial we present a cross-level compliance testing and verification approach for RISC-V that brings together Virtual Prototypes (VPs) and Register-Transfer Level (RTL) designs. The main idea is to leverage the VP for test-case generation and comparison with the RTL design. A VP is essentially an abstract model of the entire HW platform and predominantly created in SystemC Transaction-Level Modeling (TLM). VPs are leveraged for SW execution early in the design flow and thus enable parallel development of HW and SW. Thus, SystemC-based VPs provide an industry-proven approach for analysis of complex HW/SW interactions (and other system-level use cases such as design space exploration or power/timing/performance validation). In addition, the VP serves as reference model for subsequent design flow steps. A central component of the VP is the Instruction Set Simulator (ISS), which is an abstract model of the CPU (and hence responsible to fetch, decode and execute instructions one after another).

For compliance testing we present two complementary approaches for test-case generation that target positive and negative testing. First, we present a specification-based approach for generation of high-quality compliance test-suites for positive testing. Starting point is a specification that essentially consists of two parts: a set of instruction constraints that describe valid instructions, and a set of coverage requirements that the final test-suite should satisfy. The specification is passed to a generator that leverages an SMT solver to automatically generate a test-suite that satisfies all constraints and coverage requirements. In addition, we present a fuzzing-based test-suite generation approach to complement the specification-based approach with negative testing. Therefore, we leverage state-of-the-art fuzzing techniques (based on LLVM libFuzzer) to iteratively generate test-cases which are executed on a RISC-V ISS and guide the fuzzing process through the observed code coverage of the ISS. A filter is integrated between fuzzer and ISS to conservatively remove test-cases with infinite loops and platform specific details, to avoid spurious signature mismatches and to enable automated compliance testing. To further improve the fuzzing effectiveness, we incorporate a custom coverage metric and fuzzing mutator. In combination, our approaches offer a strong compliance testing framework. We found new bugs and mismatches in several RISC-V simulators including riscvOVPsim from Imperas, which is the official reference simulator for compliance testing.

To complement compliance testing, we present a cross-level co-simulation approach for verification. At the heart of this approach is an instruction stream generator that generates new instructions on-the-fly during the simulation. This enables a very efficient and comprehensive generation of instruction streams. We provide a testbench that feeds the generated instructions to the ISS and RTL core in a co-simulation based setting. The ISS and RTL core state is compared after each executed instruction in order to detect errors in the RTL core immediately when they occur. We evaluate our cross-level verification approach on the 32 bit pipelined RISC-V core of MINRES The Good Folk (TGF) Series.

Speakers:
Vladimir Herdt - DFKI GmbH Bremen
Daniel Große - Johannes Kepler University Linz
Eyck Jentzsch - MINRES Technologies

Biographies

Vladimir Herdt received the M.Sc. degree in computer science from the University of Bremen, Germany, in 2014. Afterwards, he started as a PhD student with the Group of Computer Architecture. In 2020, he received the Dr.-Ing. degree in computer science from the University of Bremen. Since 2020, he is Senior Researcher at the German Research Center for Artificial Intelligence (DFKI) / University of Bremen. His current research interests include virtual prototyping as well as verification and analysis techniques with a particular focus on RISC-V. In these areas he published more than 30 peer-reviewed journal and conference papers with a Best Paper Award at the FDL. He is recipient of the Springer BestMasters award.

Daniel Große is a Full Professor at the Johannes Kepler University Linz, Austria. He received the Dr.-Ing. degree in Computer Science from the University of Bremen in 2008. He remained as a Post-Doctoral Researcher in Bremen. In 2010, he was a substitute Professor for computer architecture with Albert‐Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. Since 2015, he has been a Senior Researcher with the University of Bremen, at the German Research Center for Artificial Intelligence (DFKI), and the Scientific Coordinator of the Graduate School of System Design, funded within the German Excellence Initiative. In July 2020, he became a Full Professor at the Johannes Kepler University Linz, Austria, where he is the head of the Institute for Complex Systems. His research interests include verification, virtual prototyping, debugging, and synthesis. He published over 140 papers in peer-reviewed journals and conferences. Dr. Große served in program committees of numerous conferences, including ASP-DAC, DAC, DATE, ICCAD, CODES+ISSS, FDL, and MEMOCODE. He received best paper awards (FDL 2007, DVCon Europe 2018, ICCAD 2018 and FDL 2020) as well as business-related awards (IKT Innovativ award 2013, Weconomy-award 2013, and Embedded Award 2014).  He is an IEEE Senior Member and an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group.

Eyck Jentzsch is the general manager of MINRES Technologies GmbH. He  holds a Dipl-Ing. from the Technical University Ilmenau and has more than 25 years experience in microelectronics and semiconductor design. His primary focus is on virtual platform modelling, development, and application but also on generation of synthesizable hardware descriptions and IP esp. in the area of RISC-V. Prior to that he worked at Cadence Design Systems Inc. and Siemens in various full- and semi-custom as well as system level design and verification positions.


 

Tutorial 4.1 Automotive Virtual Prototypes

Organizer:
Manfred Thanner - NXP Semiconductors

In this tutorial, we share our experience with deploying virtual prototypes in the automotive supply chain. We focus on the collaboration between semiconductors, Tier1, and OEMs as well as the enabling tool ecosystem.

We briefly outline the impact of virtual prototyping on the automotive development process and the required abstraction levels for the different virtual prototyping use cases. We outline the challenges of distributing virtual prototypes upwards through the automotive supply chain, with models and SW content becoming more complex in every step. Each of the presenters shares his experiences, covering aspects like modeling, Software development use-cases, as well as technological and organizational benefits and challenges.

We close with our perspective on the required close partnership and alignment along the development path to achieve a successful deployment of virtual prototypes in the automotive supply chain, enabling a “shift-left” and more productive collaboration across different teams and companies.

Speakers:
Manfred Thanner - NXP Semiconductors
Ingo Feldner - Bosch
Sacha Loitz - Continental
Ralph Schleifer - Car.Software Organisation
Kevin Brand - Synopsys

Biographies

Manfred Thanner, Senior Manager, from NXP is responsible for automotive virtual prototypes and model based architectural system level analysis in the Central System Architecture organization. He is responsible for virtual platform development programs and it’s deployment in the pre-silicon phase. Main interest is the Electronic System Level Design for automotive application and in the software processes for model based design and HW/SW co-design. Prior to NXP he worked with Freescale, Motorola and Robert-Bosch GmbH.

 

Ingo Feldner is a Project Lead for Virtual Hardware Platforms in the Central Corporate Research Division at Robert Bosch GmbH where he is dealing with the deployment of virtual platforms for productive use for different business units inside Bosch. Ingo studied technical computer science at the University of Mannheim where he first got in touch with System-Level Design and abstract models of hardware. After his diploma in 2004 he started his career at IBM Germany as a Circuit Design Engineer for IBM mainframes. In 2007 he transitioned to Bosch where he worked as a technical engineer exploring the application of virtual prototypes for different use-cases together with internal customers. Ingo has worked with virtual platforms from various semiconductor vendors and commercial and non-commercial tool environments in the field. Inside the Corporate Research Department Ingo and his team serve as a technical contact for applying virtual prototypes from very high-level abstract models down to hybrid RTL scenarios supporting the business unit use-cases.

Sacha Loitz, Continental AG, is responsible for IC virtual prototype development and deployment within the business area “Autonomous Mobility and Safety” of Continental. He has 10 years of experience with virtual prototypes covering development and support of digital as well as Analog/Mixed-Signal systems from early architectural exploration through post silicon use-cases. Sacha holds a PhD from TU Kaiserslautern, Germany for his work on formal hardware verification.

 

Ralph Schleifer, Car.Software Organisation, holds a Senior Manager position for Virtual Development within the Intelligent Cockpit and Body organization where he is establishing virtual development methodology on different abstraction levels along the automotive supply chain. He has been active in various areas of Virtual Development for more than 10 years. Before joining Audi in 2015 and now Car.SW Organisation in 2020, Ralph has been active in various areas of mobile communication at Ericsson in SW development, speech processing research, system engineering and DSP sub systems. Before joining the automotive industry, Ralph has built up a cross site virtual platform team together with colleagues in Sweden starting in 2009. The team delivered the virtual platform to enable pre silicon SW development for LTE modem ASICs.

Kevin Brand, Synopsys Inc., Sydney, Australia. Kevin is a Senior Manager of Applications Engineering at Synopsys. He has been in the field of virtual prototyping for 15 years. With a strong focus on automotive, he has been working in R&D and, in more recent years, directly enabling and deploying virtual prototyping solutions at semiconductor, Tier 1, and OEM companies. Prior to working with Synopsys Kevin worked in the Avionics and Defense Industry as a hardware engineer and holds a master’s degree in electronic design from Napier University, Edinburgh, Scotland.

 


 

Tutorial 2.2 Congestion Prediction: Deep Learning on Chip Design Enabling System

Organizer:
Singla Sahil - Infineon Technologies

Accurate congestion prediction, early in the design implementation has always been a challenge. Designers rely on their past experience to judge the quality of the floorplan. This iterative approach has higher probability to re-set the floorplan at the later stage of implementation, which approximately takes 2-3 weeks of rework. Traditional approach uses EDA simulation tools to accurately find congestion, but takes up to few weeks. Conditional Generative Adversarial Network (CGAN), is a deep learning based approach used to solve the above problem, which is independent of any EDA tool and only take few seconds to generate the result. GAN is a machine learning model in which two neural networks, i.e. Generator and Discriminator, competes with each other to become more accurate in their predictions. In GAN, there is no control over modes of the data to be generated. The CGAN changes that by adding the label y as an additional parameter to the generator and learns to generate the corresponding images. Floorplan image, Cell and Pin Density values acts as an input to the CGAN, which maps it to the corresponding Congestion Map image. The congestion map layers are M1-M4 and M1-M5. Cell, Pin Density is a set of values {Low, Medium, and High}. Congestion maps are directly correlated to the cell and pin density values. Mean Square Error and Structural Similarity Index has been used to measure the model performance.

This approach reduced the congestion prediction time from some weeks to just few seconds, which can further be reduced depending upon the hardware computation speed. A designer can just upload the floorplan image and gets congestion map in real time based upon cell and pin density values. The approach used in this study is very generic and can be applied to other key targets in the physical design cycle e.g. IR drop prediction.

Speakers:
Singla Sahil, Anand Anshuman, Bhogal Jaskaran - Infineon Technologies

Biography

Sahil Singla, Data Scientist, Infineon Technologies, Bengaluru, India

Sahil is a Computer Engineer graduate and joined Infineon Technologies in July 2018 as a Data Scientist and is responsible for developing deep learning solutions in semiconductor manufacturing and the physical design domain. He also contributed in establishment of Machine Learning team in Infineon India.

 


 

Tutorial 3.2 Introduction to AI – A Practical Overview

Organizer:
Chen Admati - Intel

AI and machine learning hold great potential to transform the enterprise, yet adoption and success rates of AI projects at the enterprise have room for improvement.

This AI tutorial was built specifically for leaders based on ten years of experience in productizing AI at Intel. In this tutorial, you will:

  • Become acquainted with AI & ML concepts 
  • Learn about AI applications & success stories at Intel
  • Get some practical best practices on how to How to run a successful AI project

 

Speaker:
Chen Admati - Intel

Biography

Chen Admati, Head of Product & Strategy, IT Data and AI, Intel

AI manager at Intel, founder and head of the healthcare at Intel’s AI unit. Brings 15 years of experience in leading and managing AI products. Staff member of IT Data and AI unit.

 

 


 

Tutorial 1.3 Application Optimized HW/SW Design & Verification of a Machine Learning SoC

Organizer:
Russell Klein - Mentor, A Siemens Business

Today, many embedded systems embody algorithms that were originally developed as software on general purpose computers. For example, an audio wake-word recognition algorithm or a video object recognition program. However, due to application (product) constraints, these algorithms usually cannot be run as software on embedded processors – they simply will not meet the performance or power requirements of the system, the algorithm needs to be accelerated with greater power efficiency.

Transforming an algorithm from software to a fast and efficient hardware implementation is a challenging task. Ensuring that the functionality is not compromised as development progresses is critical. Often, not all of the algorithms are appropriate to be implemented in hardware, resulting in a need to design both the hardware and the software in concert.

This tutorial walks through the process of migrating an algorithm from generic software to a hardware implementation customized to the specific requirements of your system; making intelligent trade-offs between hardware and software along the way. It will explain the tools and techniques needed to go from “Software to Systems” and cover a broad range of solutions including simulation, emulation, prototyping and High-Level Synthesis to design and verify SoCs and the software that runs on them.

The tutorial will use an example algorithm of an AI/ML object classification accelerator that takes a live camera feed and overlays bounding boxes and labels of objects classified in the feed. It can classify 20 objects and will be implemented as a combination of hardware and a software application running on a complete embedded Linux stack. This tutorial will cover everything from traditional UVM RTL verification to complex HW/SW verification to running real AI workloads and integration with AI/Deep Learning Frameworks such as TensorFlow.

Speakers:
Russell Klein - Mentor, A Siemens Business

Biography

Russell Klein is a Technical Director in Mentor Graphics' High-Level Synthesis Division currently working on algorithm acceleration using High-Level Synthesis. He has published a number of papers on system design and optimization. He holds several of patents for EDA tools in the area of SoC design and verification. Mr. Klein has over 25 years of experience developing design and debug solutions which span the boundary between hardware and software.  He has held various engineering and management positions at several EDA companies.

 

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Tutorial 2.3 Meeting ISO 26262 Functional Safety Targets Through Static and Dynamic Fault Analysis.

Organizers:
Jamil Mazzawi, Sesha Sai Kumar C.V., Nael Qudsi – Optima Design Automation

Meeting today’s Functional Safety Targets is posing new challenges for design teams working on automotive and other safety-critical chips at all, ASIL-A to -D, risk levels.

Even the parts of the design with the lowest ASIL A and B safety goals need some level of analysis, such as sizing different failure modes and making sure the implemented safety mechanisms at least has reasonable coverage potential. For the most safety conscious ASIL-D designs, permanent fault requirements are very stringent, and transient fault analysis must also be considered.

Eliminating transient faults can require additional hardware, in the form of hardened flip flops, which increase power consumption and silicon area especially when applied across the device. With accelerated fault analysis and the judicious use of statistical and dynamic methods, it is now possible to carefully select the appropriate flips flops for hardening to achieve ASIL D metrics while minimizing the impact on silicon real estate and power consumption. This can make a dramatic difference to the overall specific for the final device.

This tutorial will first guide attendees through the use of high-performance static fault analysis and characterization methods for all ASIL levels. It will then turn its attention to transient fault inspection and demonstrate exactly the analysis required to produce this minimal set of hardened flips flops. Attendees will be provided a full overview of the use of these techniques that can potentially save weeks in their next ISO 26262 or other safety critical design.

Speakers:
Jamil Mazzawi, Sesha Sai Kumar C.V., Nael Qudsi – Optima Design Automation

Biographies

Jamil Mazzawi, President and Chief Executive Officer

Jami Mazzawi has over 25 years’ experience in the semiconductor and EDA industries across Silicon Valley, Israel, and Europe. He has held engineering, sales, and managerial positions at Ornet Data Communication, Verisity, Rambus, Sun Microsystems, Jasper Design Automation, and now Optima. With a successful track record developing, promoting, and selling disruptive technologies that include advanced verification solutions and leading automotive development products, Jamil authored seven patents in related fields. Jamil is also the director and co-founder of the Nazareth Startup Company Forum (NSCF) promoting Arab-owned startup companies in Israel. He holds a B.Sc. in Computer Engineering from the Technion, Israel and an MBA from San Jose University, CA.

Sesha Sai Kumar C.V., Director of Application Engineering

Sesha Sai Kumar C.V has more than 25 years of rich VLSI eco-system experience from Concept to Chip. Started his career as a Scientist in India’s Defence RnD, he worked at Synopsys, LSI Logic, ArchPro (acquired by Synopsys). He worked on Applications Engineering in the field of, Functional Safety and Fault Campaign, Low Power VLSI verification, Clock Domain Crossing, Concept to Chip Digital Designs, and VLSI education.  Sesha has co-founded SkandVLSI, introducing a Learn-Practice-teach platform called VGuru Verilog/VHDL with interactive guidance for university undergrads. He holds a BTech in Electronics and Communications Engineering from SV University, India.

Nael Qudsi, Optima Design Automation, Director of Engineering

Nael Qudsi is responsible for Optima Design Automation’s engineering team, developing the next generation of Functional Safety fault analysis technology as well as streamlining related methodologies. Prior to Optima, Nael held both technical and management positions at Jasper Design Automation, later acquired by Cadence Design Systems. There he worked on advanced formal technologies, including safety analysis products, as part of the popular JasperGold formal tools. As a research assistant Nael leveraged his expertise in parallel multithreaded compilers and automated Boolean optimization methods. Nael has also worked as a cyber security consultant for multiple organizations. Nael holds a B.Sc. in Computer Science from Haifa University in Israel.

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Tutorial 3.3 Beyond Bug Hunting: Verification Coverage from Safety to Certification

Organizers:
Rob van Blommestein - OneSpin Solutions

Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Common simulation metrics are imprecise and only measure control coverage resulting in significant lack in verification quality. These remedial practices are time-consuming and leave undetected bugs that could significantly impact design safety. Mutation analysis takes the risk out achieving safety signoff. Results and accurate and reproduceable and creates reliable identification of verification gaps by highlighting over-constraining, dead and redundant code.

This tutorial will explore how mutation analysis can have a positive impact on the safety of your design and provide signoff confidence needed to achieve proper safety certification.

In addition, the tutorial will show how to achieve a meaningful integration of formal and simulation coverage metrics. A long-standing wish of many verification engineers and managers, coverage integration reduces effort overlap between simulation and formal, and enables faster, more rigorous signoff.

Speaker:
Nicolae Tusinschi - OneSpin Solutions

Biography

Nicolae Tusinschi is Product Specialist Design Verification at OneSpin Solutions. Nicolae has an exhaustive knowledge of design verification methodologies and is part of the OneSpin 360 DV™ design verification solution product team. Nicolae holds a European Master's in Embedded Computing Systems (EMECS) awarded jointly by Technische Universität Kaiserslautern (Germany) and University of Southampton (United Kingdom).

 

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Tutorial 1.4 Boost your Productivity in FPGA/ASIC Design and Verification

Organizer:
Bart Brosens - Sigasi

Most EDA tools take your HDL code as a starting point and process it as efficiently as possible, focusing on the silicon. But those tools do not care about how you come up with this code in the first place.

If you want to be more productive as a hardware design or verification engineer working on VHDL, Verilog and SystemVerilog code, you deserve a software tool that helps you to create and explore code in a more efficient way. Lessons learned from designing complex software systems also apply to designing complex hardware systems.

In this tutorial, Bart Brosens (Application Engineer at Sigasi) will demonstrate how to increase your productivity using an IDE for your HDL design. You’ll learn our best practices from proven methodologies such as:

  • type-time feedback,
  • intelligent content assist,
  • various ways to explore and navigate through large projects,
  • how to effortlessly document your design
  • and much more.

 

Speaker:
Bart Brosens - Sigasi

Biography

Bart Brosens, Application Engineer, Sigasi ny

Kids need a passion in life and Bart’s passion was always electr(on)ic devices. His talent in hardware design has transformed into a career in companies like Target Compiler Technologies (now Synopsys), Barco (now Silex Insight), Easics and now Sigasi.

At Sigasi, Bart was first a customer and is now our senior Application Engineer supporting customers from Korea to California, and most countries in between. When he’s not talking to Sigasi’s clients, Bart loves to sing in a choir, take long mountain hikes with his family or engage himself in local social activities in his neighbourhood.

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Tutorial 2.4 Using Simulation Acceleration to Speed Block and Platform Level IP Verification

Organizer:
Fabian Delguste - Synopsys

Design complexity growth has inspired new techniques to accelerate digital simulation of circuits by taking full advantage of high-performance verification platforms available. Latest techniques include fine-grained parallelism, which can significantly reduce simulation turn-around time by automatically partitioning the design to execute on multiple processor cores, and simulation acceleration, which accelerates the verification of block and platform level IP by integrating fast simulation with the specialized, high-performance hardware provided by fast emulation systems.

This tutorial reviews novel simulation acceleration technology for Synopsys VCS and how it will enable verification engineers to speed up the digital simulation of standard UVM testbenches, including all existing verification requirements, through the seamless integration of VCS and the Synopsys ZeBu Server emulation system. The tutorial will present the use models and basic tool options required to enable simulation acceleration within a regular VCS environment, the SystemVerilog constructs used, and the available debug and profiling capabilities. For different verification needs, we will analyze how the different constructs and use-models provide trade-offs between ease of use, simulation performance and hardware utilization.

Speaker:
Fabian Delguste - Synopsys

Biography

Fabian Delguste, Applications Engineer, Verification Group, Synopsys

Fabian has been in the industry for 20+ years. He has expertise in SW development, HW design and EDA. He is in charge of a team of AEs in Europe. His charter is to deploy emulation and prototyping solutions to key accounts in Europe. Fabian holds a MSEE and graduated from “École Polytechnique de l'Université de Nantes”.

 

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Tutorial 3.4 Using Models to Shift-Left Verification and Enable Verification IP Re-use Throughout the Design Flow

Organizers:
Baruch Mitsengendler, Cristian Macario, MathWorks

The shrinking of the design cycle time and the need for zero bugs, is forcing the semiconductor industry to rethink its design flows. Particularly important are the abilities to catch bugs as early as they are introduced, to avoid long iteration cycles.  Of similar importance is the Reuse of design models and verification IPs throughout the different steps of the development flow.

In this presentation we will show how MATLAB and Simulink are used by many leading semiconductor companies to quickly model their systems and IPs and to start verification at behavioral model level by defining test cases, linking them to requirements and measuring coverage to assess completeness.

After that, we will present how system models and verification IPs can be reused within EDA tools like logic simulators as well as SPICE simulators. We will explore several options, like the generation of UVM test benches, the generation of SystemVerilog behavioral models as well as the co-simulation with SPICE and logic simulators.

This approach allows engineers to find bugs earlier in their development. It also enables efficient reuse, tool interoperability, and quick iterations between design steps, significantly reducing the overall development time.

Who should attend?

Systems Engineers and Verification Engineers (both Digital and Mixed-Signal).

Speakers:
Baruch Mitsengendler, Cristian Macario, MathWorks

Biographies

Baruch Mitsengendler works with MathWorks, Germany since October 2016 as a senior application engineer. His main functions include responsibility for the different HDL related toolboxes. Prior to joining MathWorks, Baruch was working as an ASIC design and verification engineer, both in Israel and Germany. His main working focus was wireline communication systems as well as memory products. Baruch has a B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology.

Cristian Macario, Communications, Electronics and Semiconductor Industry Manager – EME, MathWorks. Cristian Macario joined MathWorks in November 2018 and is responsible for the MathWorks communications, electronics and semiconductor business across the EMEA region. Working with MathWorks customers, he enables them to fully tackle their challenges by improving their workflows and using the full capabilities of MathWorks products. He also helps MathWorks staying aligned with the needs of the Semiconductor Industry. Cristian is based in Munich, Germany. Before his current role, Cristian was at NXP Semiconductors, where he worked as System-on-Chip (SoC) design and verification engineer in the Automotive Microcontroller division. Here he established the UVM verification methodology, worked on SoC integration and designed a Network-on-Chip interconnect. Prior to this, he worked at LSI Corporation as SoC verification engineer and at ARM as CPU designer. Cristian holds a master’s degree in Electronic Engineering from Politecnico di Torino, Italy.

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Tutorial 4.4 Analysis and Verification of Safety Critical E/E Systems and Circuits

Organizer:
Alessandra Nardi - Cadence Design Systems

E/E systems and circuits deployed in safety critical application introduce additional metrics that quantify the likelihood of failure and the ability of the device under consideration to detect (and potentially correct) faulty behaviors. These metrics needs to be calculated and verified by Functional Safety (FS) analysis and verification techniques. In addition to specific analysis and verification challenges, the process development lifecycle for safety-critical applications is also rigorous in terms of traceability requirements throughout the distributed supply chain.

The tutorial covers an introduction to FS analysis and lifecycle development and evolves into an introduction of FS verification with a focus on fault injection and its associated challenges and potential solutions.

Speakers:
John Hayden, Analog Devices
Jason Campbell, NVIDIA

Biographies

John Hayden of Analog Devices Inc. has worked in the semiconductor industry since 1985. His experience includes digital and mixed-signal design of complex SoCs (Systems On Chip) and SiPs (Systems In Package), including systems with multiple embedded processor cores and with firmware and software components. He has led safety-relevant product designs since 2011 in the industrial (IEC 61508) and automotive (ISO 26262) domains. He has concentrated full-time in automotive functional safety engineering since 2016. John presently manages ADI's central Automotive hardware functional safety team, and is ADI's corporate representative to the US TAG for ISO TC22/SC32/WG8 (standards body for ISO 26262) and to the Accellera Functional Safety WG. John holds 6 patents in digital and processor architectures and safety-related systems.

 

Jason Campbell is a member of the Functional Safety Tools Group at NVIDIA where he is responsible for fault simulation tools and methodologies. Jason has over 30 years of experience in EDA tool development including 20 years’ experience with fault simulation. He has been the lead architect of many widely used EDA tools including VirSim, VeriCov/HDL Score and Z01X. Prior to joining NVIDIA Jason worked at Gateway Design Automation, Simulation Technologies (VP Engineering/founder), Summit Design, Provis, WinterLogic (CEO/founder) and Synopsys. Jason holds a BS in Software Engineering from the University of Minnesota Institute of Technology.