29 - 30 October, 2019

Holiday Inn Munich City Centre

Munich, Germany

Event Details

MP Associates, Inc.

WEDNESDAY October 24, 4:00pm - 5:30pm | Forum 5

Tutorial 14 - Hardware and Software Co-verification in Hybrid HDL Simulation and Emulation Environment with QEMU

Krzysztof Szczur - Aldec, Inc.
Radoslaw Nawrot - Aldec, Inc.
Krzysztof Szczur - Aldec, Inc.

The FPGA or ASIC SoC require a robust pre-silicon hardware/software co-verification platform. Developing device drivers in pure HDL/RTL simulation environment would be counterproductive and developing or testing embedded operating system and application stack impossible. Virtual platforms and virtual machines have been used by software developers as a high-speed simulation vehicle but they are only appropriate with standard components like CPU, memory, timers and the like. The challenge emerges when custom IP-core is added to the design. Lack of virtual models for custom IP blocks or off-chip devices is a common drawback and the obstacle to complete firmware validation in pure virtual platform and before silicon tape-out. Hybrid co-simulation and then co-emulation of custom HDL blocks with CPU subsystem simulated as virtual machine bridges this gap in verification environment. QEMU is a generic and open source machine emulator that supports various computer hardware architectures including Intel x86 and ARM® Cortex® families. It can be connected with Aldec’s Riviera-PRO™ high performance HDL simulator and HES-DVM™ the FPGA based emulation platform to provide a hybrid co-simulation and co-emulation environment for early hardware/software co-verification and embedded software development.

In this tutorial we will demonstrate the latest QEMU Bridge designed to provide connection between virtual machine of CPU subsystem in QEMU and custom hardware designed in VHDL or Verilog which is simulated in Riviera-PRO or emulated in the HES FPGA board. We will also show how software debugger (GDB) can be used in step-lock mode with the Aldec Hardware Debugger to provide holistic view into the entire SoC and so facilitate debugging typical problems that are resulting from design specification being misunderstood by either software or hardware developers or last minute changes introduced in this specification. The QEMU Bridge was designed to integrate with the latest QEMU version that can be obtained from the official github and is extended with the co-simulation and co-emulation hooks by applying Aldec’s patch that modifies PCI device tree in QEMU virtual machine. During the tutorial we will explain and discuss the integration layer as well as the functionality of the environment with the benefits it brings to hardware and software verification teams.

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