October 26-27, 2021
Virtual Conference

Welcome to DVCon Europe 2021!

Exhibit & Sponsor Prospectus Now Available!

Deadline: September 17, 2021

The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation or integration. It is a place where the latest methodologies and technologies for the industrial use of tools, languages, and standards for integrated and embedded systems and products are shared and discussed.

The conference covers the application of standards, methodologies, and flows for system-level, hardware and software design, verification, validation, design automation and IP reuse.

Industry applications of interest include (but not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. DVCon Europe solicits submissions related to advanced design and verification on special interest areas such as Digital Twin, Machine Learning, Internet-of-things, Functional safety and security, AI, ADAS and digitalization. 

DVCon Europe 2021 accepts submissions of papers, tutorials and panels with highly technical content reflecting real life experiences. Topics include (but are not limited to): System Level and Software Design, Model-Based and Model Supported Software Design, Verification & Validation, IP Reuse & Design Automation, Functional Safety and Security, and Mixed-Signal & Low-Power Design and Verification.

Mark your Calendars

Important Dates

July 26, 2021

Full Paper Due

September 13, 2021

Author Notification about Full Paper Submission

September 20, 2021

Accepted Papers: Camera Ready Copies, Copyright Form & Video Presentation Due

August 11, 2021

SystemC Evolution Day 2021 – Call for Contributions is now open!

Possible Submissions

Example Topics

SYSTEM-LEVEL & SOFTWARE DESIGN
  • Virtual prototyping and Digital Twins
  • Transaction-level modeling (e.g., SystemC TLM)
  • Hardware-assisted prototyping
  • Hardware/software/embedded co-design
  • Machine Learning
MODEL-BASED & MODEL SUPPORTED SOFTWARE DESIGN
  • Software for verification
  • Software development and verification
  • Model based software design
  • Low level software design and verification
  • Model based tools and techniques for application level software.
IP REUSE & DESIGN AUTOMATION
  • High-level synthesis from ESL languages
  • Interoperability of models and/or tools
  • IP tagging, protection or security
  • SoC and IP integration methods, flows, and tools
  • Configuration management of IPs including different abstraction level
  • Flow and tool automation (e.g., IP-XACT)
VERIFICATION
& VALIDATION
  • Verification process, reuse and resource management
  • Methods bridging between verification and validation
  • Hardware/software co-verification
  • Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs)
  • Formal and semi-formal V&V techniques
FUNCTIONAL SAFETY & SECURITY
  • Methods and flows for functional safety standard compliance (e.g., ISO 26262, DO-254)
  • Safety and security in verification and validation
  • Requirements-driven design and verification including traceability
  • New methods and tools supporting functional safety and security
MIXED-SIGNAL & LOW-POWER DESIGN & VERIFICATION
  • AMS modeling for concept and system-level design
  • Application of mixed-signal extensions in verification (e.g., UVM-MS)
  • Real-number modeling approaches
  • Self-checking testbenches in analog verification
  • Low-power design and verification (e.g., UPF)

Our Blog

Latest Articles

SystemC Evolution 2021

In addition to the Accellera SystemC Evolution Day, we are continuing the SystemC Evolution with smaller, regular, workshops. We refer to these workshops as fikas (Swedish,

Read More »

Get your Avatar ready!

The 2020 edition of the Design and Verification Conference & Exhibition Europe is just a day away – the conference takes place on October 27-28, 2020. But

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Publications

Recently Published

EENews Europe:

Discovering Deadlocks in Memory Controller IPs

Author:
Jef Verdonck

DVCon Europe 2020 Best Paper:

Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level


Authors:
Michele Chilla & Leonardo Gobbi, Qualcomm Ireland

DVCon Europe 2020 – Best Poster:

Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing

Authors:
Ping Yeung, Mark Handover, & Abdel Ayari, Siemens EDA

Photo Gallery

From Previous Years