The Test Bench Factory: Building Verification Environments Faster, Better, Smarter
Thorsten Dworzak, Infineon Technologies AG
Johannes Grinschgl, Infineon Technologies AG
AND
Simulation Time Federation using the Zenoh framework between SystemC's and QEMU
Mark Burton, Qualcomm
Mahmoud Kamel, Qualcomm
Alwalid Salama, Qualcomm
Minimally Intrusive Safety and Security Verification of Rust RTIC Applications
Pawel Dzialo, Luleå University of Technology
Ivar Jönsson, Grepit AB
Malte Munch, Luleå University of Technology
Erik Serrander, Grepit AB
Johan Eriksson, Grepit AB
Per Lindgren, Luleå University of Technology
Harnessing a Digital Twin for Personalized Type-1 Diabetes Care: A Model for Glucose Control and Insulin Administration
Ammar Abdelghany, Cairo University
Asmaa Khaled, Cairo University
Nada Alfowey, Cairo University
Mohamed Hamed, Cairo University
Hanan Tawfik, Cairo University
Tamer Basha, Cairo University
Loai Ali, Siemens Digital Industries Software
Mohamed Abdelsalam, Siemens Digital Industries Software
Addressing Fixed-Point Format Issues in FPGA Prototyping with an Open-Source Framework
Vishal Chovatiya, Infineon Technologies
Gabriel Rutsch, Infineon Technologies
Wolfgang Ecker, Infineon Technologies
Virtual Prototyping Framework for Pixel Detector Electronics in High Energy Physics
Francesco E. Brambilla, CERN, Geneva, Switzerland
Davide Ceresa, CERN, Geneva, Switzerland
Jashandeep Dhaliwal, CERN, Geneva, Switzerland
Stefano Esposito, CERN, Geneva, Switzerland
Kostas Kloukinas, CERN, Geneva, Switzerland
Jeffrey Prinzie, KU Leuven, Leuven, Belgium
Formal RTL Sign-off with Abstract Models
Lucas Deutschmann, RPTU Kaiserslautern-Landau
Osama Ayoub, LUBIS EDA
Rohith Batthineni
Michael Schwarz
Tobias Ludwig, LUBIS EDA
Dominik Stoffel
Wolfgang Kunz, Infineon Technologies AG
The Three Body Problem: There’s more to building Silicon than what EDA tools currently help with
Peter Birch
VyperCore
Ben Marshall
PQShield
Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging
Prof. Dr. Freddy Gabbay PhD
Ruppin Academic Center, Israel
Firas Ramadan & Majd Ganaiem
Technion – Israel Institute of Technology
A Generic Configurable Error Injection Agent for On-Chip Memories
Anil Deshpande, Niharika Sachdeva, Arjun Suresh Kumar, Damandeep Saini, Ravi Teja Gopagiri, and Somasunder KS
Samsung Semiconductor India R & D Centre(SSIR)
Jaechul Park
Samsung Electronics, Korea
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development
Harshal Kothari, Vinay Swargam, Sriram Kazhiyur, Sounderrajan
Somasunder, and Kattepura Sreenath
Testbench Flexibility as a Foundation for Success
Ana Sanz Carretero,
Katherine Garden, and Wei Wei Cheong
Xilinx
An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure
Caglayan Yalcin &
Aileen McCabe
Qualcomm
Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level
Michele Chilla & Leonardo Gobbi
Qualcomm
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”
Ping Yeung, Mark Handover, and Abdel Ayari
Siemens
