Awards

Addressing Fixed-Point Format Issues in FPGA Prototyping with an Open-Source Framework

Vishal Chovatiya, Infineon Technologies
Gabriel Rutsch, Infineon Technologies
Wolfgang Ecker, Infineon Technologies
 

Virtual Prototyping Framework for Pixel Detector Electronics in High Energy Physics

Francesco E. Brambilla, CERN, Geneva, Switzerland
Davide Ceresa, CERN, Geneva, Switzerland
Jashandeep Dhaliwal, CERN, Geneva, Switzerland
Stefano Esposito, CERN, Geneva, Switzerland
Kostas Kloukinas, CERN, Geneva, Switzerland
Jeffrey Prinzie, KU Leuven, Leuven, Belgium
 

Formal RTL Sign-off with Abstract Models

Lucas Deutschmann, RPTU Kaiserslautern-Landau 
Osama Ayoub, LUBIS EDA 
Rohith Batthineni
Michael Schwarz
Tobias Ludwig, LUBIS EDA 
Dominik Stoffel
Wolfgang Kunz, Infineon Technologies AG 

A Generic Configurable Error Injection Agent for On-Chip Memories

Anil Deshpande, Niharika Sachdeva, Arjun Suresh Kumar,  Damandeep Saini, Ravi Teja Gopagiri, and Somasunder KS
Samsung Semiconductor India R & D Centre(SSIR)

Jaechul Park
Samsung Electronics, Korea

A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

Harshal Kothari, Vinay Swargam, Sriram Kazhiyur, Sounderrajan
Somasunder, and Kattepura Sreenath

Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level

Michele Chilla & Leonardo Gobbi
Qualcomm

Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”

Ping Yeung,  Mark Handover, and Abdel Ayari
Siemens