Session 1A

Automated Design Behaviour Extraction of SoC Interconnects Using Formal Property Verification
- Jan Hahlbeck, Chandana Guddenahalli Palaksha and Görschwin Fey
Verification for Everyone
- Noel McCarthy and Paul Wright

Session 1B

Simulation States
- Mark Burton, Mark Glasser, Karsten Einwich and Ramzi Karoui
CPAS : Cocotb Power Aware Simulation Framework
- Ahmed Alsawi, Liam O'Reilly and Evin Hughes

Session 1C

Synthesis Strategy for Standard Cell Library Validation
- Hyeonyoung Shin, Sanggi Do and Jinho Lee

Session 1D

Analogous Alignments: Digital "Formally" meets Analog
- Hansa Mohanty and Deepak Gadde
Functional Coverage Sign-off assisted by Formal Connectivity
- Asheque Mohammad Zaidi and Muhammad Ul Haque Khan

Session 1E

Verifying Non-friendly Formal Verification Designs: Can We Start Earlier?
- Bryan Olmos, Daniel Gerl, Aman Kumar and Djones Lettnin
A Novel Approach for HW/SW Co-Verification: Leveraging PSS to Orchestrate UVM and C Tests
- Tom Fitzpatrick, Vishal Baskar, Wael Mahmoud and Mohamed Nafea

Session 2A

An Innovative Approach to Verify the SoC Integration using the Formal Property Verification
- David Vincenzoni and Marcello Dusini
Making code generation favourable
- Tero Isännäinen

Session 2B

Auto Generation is the key to rapid integration to UPF-like UPVM libraries for Unified Power Verification
- Gopi Srinivas Deepala, Priyanka Gharat and Lakshay Miglani
Enhancing Automotive Security and Safety through CSEv2.0 Test Vector Validation with Synopsys MIPI CSI VIP
- Venkata Naga Srideepti Pisipati and Andrew Elias
Efficient Workflow using Verilator for Processor Benchmarking in SystemC-based Automotive SoC Platforms
- Johannes Sanwald, Andreas Mauderer, Mohammad Badawi, Javier Castillo, Jan-Hendrik Oetjens, Maryam Keeley, Tim Kogel and Andreas Wieferink

Session 2C

Single Source library for high-level modelling and hardware synthesis
- Mikhail Moiseev and Nanda Kalavai
Heartbeat based early detection of hang issues
- Vinaykumar Kori and Tejbal Prasad
Streamline PCIe 6.0 Switch Design with effective Verification strategies
- Deep Mehta, Meghvendra Rathod, and Nicolas Dai

Session 2D

Solving verification challenges for complex devices with a limited number of ports using Debugports
- Shyam Sharma and Shravan Soppi
Functional Verification Using C Model: DPI-C VS Static Value Tables
- Djordje Velickovic and Katarina Bozinovic
A new approach to integrated AI into analog/mixed-signal verification workflow
- Long Hoang, Emanuel Popovici and George Duffy

Session 2E

A lightweight Python framework for analogue circuit design, optimisation, verification and reuse
- Wolfgang Scherr, Violeta Petrescu, Johannes Sturm, Dirk Hammerschmidt and Santiago Sondon
Safety Analysis of Automated Driving Platforms Using Digital Twin Simulation and Runtime Monitoring
- Tasneem A. Awaad, Hanya A. Elged, Mohamed A. Abu-Bakr, Sama Y. Fathy, Sara H. Ahmed, Mohamed Abdelsalam and M. Watheq El-Kharashi

Session 3A

Hard Math – Easy UVM: Pragmatic solutions for verifying hardware algorithms using UVM
- Mark Litterick, Aleksandar Ivankovic, Bojan Arsov and Aman Kumar

Session 3B

Retention Sufficiency Validation for Optimizing State Retention Cells in Low Power Design
- Nitesh Kalwani and Mateus Silva
A UVM Testbench for Checking the Global Convergence of Analog/Mixed-Signal Systems: An Adaptive Decision-Feedback Equalizer Example
- Jaeha Kim
Enabling True System-Level, Mixed-Signal Emulation
- Paul Wright, Nimay Shah, Pranav Dhayagude, Raj Mitra and Adam Sherer

Session 3C

uvm_objection – challenges of synchronizing embedded code running on cores and using UVM
- Joachim Geishauser, Yassmina Eliouj, Vasundhara Gontia, Sefa Veske, Shripad Nagarkar and Tobias Thiel

Session 3D

Automatic Insertion of a Safety Mechanism for Registers in RTL-Modules
- Holger Busch and Jonathan Ross
Harnessing Regenerative AI and Machine Learning for Efficient Fault Simulation
- Himanshu Vishwakarma, Ranjitha M and Lakshya Miglani
Design and Verification of SEE-Tolerant ASICs at CERN: Methodologies and Challenges
- Adithya Pulli, Matteo Lupi, Stefano Esposito, Simone Scarfi, Szymon Kulis and Xavier Llopart Cudie

Session 3E

Enable Reuse of SystemVerilog Verification IPs in cocotb/pyuvm
- Yilou Wang, Thorsten Dworzak and Johannes Grinschgl
Unleash the Power of Formal for Post Silicon Debugging
- Jan Hahlbeck and Shreya Upadhyay

Session 4A

Harnessing the Strength of Statistics and Visualization in Verification
- Olivera Stojanovic and Uri Feigin

Session 4B

Addressing Fixed-Point Format Issues in FPGA Prototyping with an Open-Source Framework
- Vishal Chovatiya, Gabriel Rutsch and Wolfgang Ecker
Compiling AI Workloads for On-Device Inference on Heterogeneous Systems using MLIR
- Jan Moritz Joseph, Maximilian Bartel and Rainer Leupers

Session 4C

Scalable and mergeable functional coverage flow for highly configurable IP signoff and specific customer deliveries
- Fryderyk Koziol and Sebastian Cieslak

Session 4D

Deployment of containerized simulations in an API-driven distributed infrastructure
- Tim Kraus, Axel Sauer and Ingo Feldner
libtcg -- Accurate lifting of executable code using QEMU
- Anton Johansson and Alessandro Di Federico

Session 4E

Improved Performance of Constraints
- Milos Pericic
UVM Portable Stimulus: Synchronized Multi-Stream Parallel-State Scenario in UVM
- Ahmed Allam